Two kinds of scan circuitry are used in integrated circuits--boundary scan and level-sensitive scan (LSSD). Boundary scan involves selectively isolating the I/O pads from the internal circuitry, applying stimulus to a shift register and applying those values to both the internal circuitry and the I/O pads, and then capturing the outputs from both the internal circuitry and the I/O pads. In this manner, boundary scan allows the I/O pads and on-chip logic circuitry to be tested independently. To facilitate this testing, the boundary scan circuitry is placed between the on-chip circuitry and the I/O pads.
IEEE Standard 1149.1-1990, "IEEE Standard Test Access Port and Boundary-Scan Architecture" (published by the Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, N.Y. 10017 USA) provides "standardized" approaches to: testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate; testing the integrated circuit itself, and observing or modifying circuit activity during the component's normal operation. This standard is well known in the art and therefore is not explained in detail herein.
Boundary scan circuitry details are dependent on the type of I/O pad in use. Each I/O pad can be characterized as being either an input pad, an output pad, a tri-statable output pad or a bidirectional I/O pad. To be able to control and observe the state on an I/O pad, at least one boundary scan bit is required for each of the above-listed I/O block types. Specifically, each input and output pad requires one boundary scan bit, each tri-statable output pad requires two boundary scan bits, and each bidirectional I/O pad requires three boundary scan bits. FIG. 1 shows the boundary scan for an input pad; FIG. 2 shows the boundary scan for an output pad; FIG. 3 shows the boundary scan for a tri-statable I/O pad; and FIG. 4 shows the boundary scan for a bidirectional I/O pad.
In the case of a tristatable I/O pad, one of the two scan bits is for the output signal, IOB.O, and the other bit is the alternate for the tristate enable signal, IOB.T. In the case of a bidirectional I/O pad, three bits are required because a bidirectional I/O pad is a combination of an input pad and a tri-statable I/O pad. One scan bit is therefore needed for the output signal, IOB.O, the second bit is the alternate for the tristate enable signal, IOB.T, and the third bit is for the input signal, IOB.I.
An alternative use for available boundary scan logic is to capture all of the user logic levels at the I/O pads into the shift register at the same time and then scan them out of the shift register serially. The capture of the data bits is performed by setting the Shift/Capture line to 0 before strobing the DRCK line, as can be seen in FIGS. 1-4.
FIG. 4 illustrates boundary scan circuitry in which all four types of I/O pads are co-resident. This commonly occurs in programmable logic devices in which the I/O pad type is determined not when the integrated circuit (IC) is fabricated, but when a designer programs the IC for a particular application. Because the I/O pad type needed by the designer is not known when the circuit is fabricated, all four types of I/O pads must be available so that the designer has full flexibility to use whatever type of I/O pad is needed for a particular application. Because all four types of I/O pads are available in each I/O pad on these integrated circuits, the scan chain must have three bits, even though perhaps not all of them will be used in every I/O pad. For example, an I/O pad that is used for input uses only the first data bit. An output pad uses only the second bit. A bidirectional I/O pad uses all three bits. An unused I/O pad uses none of the three bits, even though those bits remain in the scan chain. Thus, if all the I/O pads in a programmable logic device are connected in a scan chain, the number of data bits is always three times the number of I/O pads. This scan chain has the advantage of being the same length, no matter what the configuration of the I/O pad. But this scheme also has the disadvantage that the number of clocks required to scan all the data bits and the data storage required for these data bits is always three times the number of I/O pads, whether or not they are all used.
As indicated previously, two kinds of scan circuitry are used in integrated circuits--boundary scan and level-sensitive scan (LSSD). LSSD is a circuit testing technique which uses either a specially modified flip-flop in place of all flip-flops in a design, or places a special multiplexer in front of every flip-flop in a design. In this manner, the flip-flops in a chip's internal circuitry are converted into a shift register that includes all sequential elements in the circuit and isolates the combinational logic for testing and observation. FIG. 9 shows a circuit 900 before adding LSSD. In circuit 900, combinational logic block 901 drives flip-flops 902A-902C, and feedback lines provide the output signals of these flip-flops back to combinational logic block 901.
FIG. 10 shows how circuit 900 (FIG. 9) can be modified to incorporate LSSD. Specifically, multiplexers 1003A-1003C are added in front of flip-flops 902A-902C, respectively. The signal on Operate/Scan line 1004 determines whether flip-flops 902A-902C get their data from combinational logic block 901 or from scan chain 1005. If the signal on Operate/Scan line 1004 is a logic 1, combinational logic block 901 is connected to flip-flop input terminals, and circuit 1000 operates in the "operate" mode. On the other hand, if the signal on Operate/Scan line 1004 is a logic 0, flip-flops 902A-902C are connected in a scan chain. In this configuration, the data in the scan chain is shifted one position each clock cycle, from Scan.sub.-- In to Scan.sub.-- Out.
A first operating mode loads the flip-flop scan chain from off-chip. In this mode, the clock is cycled through enough cycles to load every flip-flop 902. Then the Operate/Scan signal is set to a logic 1. Combinational logic block 901 then operates on the data in flip-flops 902. A second operating mode off-loads the data from the scan chain to some destination outside of the chip. This mode begins in "operate" mode. When the signal on Operate/Scan line 1004 is set to logic 0 and circuit 1000 operates in "scan" mode, the data in flip-flops 902A-902C (obtained during the "operate" mode) can then be shifted up the scan chain toward Scan.sub.-- Out.
An FPGA with built-in LSSD circuitry can implement the multiplexers as a dedicated resource and leave the combinational logic for implementation in configurable logic blocks (well known structures in programmable logic devices and therefore not explained in detail herein). In this implementation, if the end-user's programmed circuit doesn't use all of the flip-flops on the FPGA, the scan chain will still contain all of the "unused" flip-flops, thereby making the scan chain longer than is necessary and increasing the time required to scan the flip-flop data onto or off of the chip.
Therefore, a need arises for improving the testing of logic circuit networks, and specifically for accelerating the testing of both boundary and LSSD scan circuitry.